Method for forming a flash memory cell having contoured floating gate surface

ABSTRACT

A floating gate for use in a memory cell is provided which comprises a first end region adjacent a first lateral end of the floating gate; a second end region adjacent a second lateral end of the floating gate opposite the first lateral end; and a middle region positioned laterally between the first and second end regions, the middle region having a vertical thickness which is less than a vertical thickness of the first end region and which is less than a vertical thickness of the second end region; wherein the floating gate is composed of a material which is formed during a single fabrication step and shaped to form the first and second end regions and middle region by one or more subsequent fabrication steps. A method is provided for forming a contoured floating gate for use in a floating gate memory cell, including forming a floating gate comprising a polysilicon layer over a substrate; forming oxide layers on opposing sides of the floating gate, the oxide layer having a vertical thickness greater than a vertical thickness of the floating gate; forming a spacer layer over the oxide layers and the floating gate; removing a portion of the spacer layer such that a top surface of the floating gate positioned laterally toward a middle region of the floating gate is exposed; and removing a portion of the floating gate underlying the exposed top surface of the middle region to form the contoured floating gate.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is a continuation-in-part of U.S. patentapplication Ser. No. 09/415,939, filed Oct. 8, 1999 (Atty. Docket No.:MXIC 1276-1) and entitled “Flash Memory Cell Having Contoured FloatingGate Surface”, which is hereby incorporated by reference for allpurposes. This application is also a continuation-in-part of U.S. patentapplication Ser. No. 09/415,936, filed Oct. 8, 1999 (Atty. Docket No.:MXIC 1326-1) and entitled “A Method for Forming a Contoured FloatingGate Cell”, which is hereby incorporated by reference for all purposes.This application is also a continuation-in-part of U.S. patentapplication Ser. No. 09/415,938, filed Oct. 8, 1999 (Atty. Docket No.:MXIC 1327-1) and entitled “A V-Shaped Floating Gate for a Floating GateMemory Cell”, which is hereby incorporated by reference for allpurposes. This application is also a continuation-in-part of U.S. patentapplication Ser. No. 09/415,788, filed Oct. 8, 1999 (Atty. Docket No.:MXIC 1328-1) and entitled “A Method for Forming a V-Shaped FloatingGate”, which is hereby incorporated by reference for all purposes.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to non-volatile digital memory, andmore particularly, to FLASH EPROM memory technology incorporatingfloating gates having reduced lateral dimensions.

[0004] 2. Description of Related Art

[0005] FLASH EPROM memory is a class of non-volatile storage integratedcircuits. In general, FLASH EPROMS have the capability of electricallyerasing, programming, or reading a memory cell on a chip. Generally, aFLASH EPROM includes a floating gate and a control gate which form anelectrical connection. A FLASH EPROM operates by charging or dischargingelectrons in the floating gate of the memory cell in a capacitativemanner. The floating gate is formed of a conductive material, typicallymade of polysilicon, which is insulated from the channel of thetransistor by a layer of oxide or other insulating material, andinsulated from the control gate or word-line of the transistor by asecond layer of insulating material.

[0006] The act of charging the floating gate is termed a “program” stepfor a FLASH EPROM. The program step may be accomplished throughso-called hot electron injection by establishing a large positivevoltage between the control gate and the source. The act of dischargingthe floating gate is called the “erase” function for a FLASH EPROM. Theerase function is typically carried out by an F-N tunneling mechanismbetween the floating gate and the source of the transistor (sourceerase) or between the floating gate and the substrate (channel erase).

[0007] Due to increasing memory demands, a need exists to further reducethe size of memory devices, such as FLASH EPROMs. Reducing the cell sizeof memory devices increases performance and reduces power consumption.

[0008] Several devices have been developed with reduced cell size. Onesuch device is described in “A Low Voltage Operating Flash Memory Cellwith High Coupling Ratio Using Horned Floating Gate with Fine HSG,” byKitamura et al., 1998 Symposium on VLSI Technology Digest of TechnicalPapers. Another example of a memory device with reduced cell size isdescribed in “A 0.24-μm Cell Process With 0.18-μm Width Isolation and 3DInterpoly Dielectric Films for 1-GB Flash Memories” by Kobayashi et al.,IEEE 97-275 (1997).

[0009] Reducing the size of a memory cell has lead to memory cells withcertain disadvantages including overbearing floating gates, orintermediate structures formed during the manufacturing of the floatinggate, which degrade the tunnel oxide layer. The formation of sharpcorners on the floating gate also leads to charge leakage.

SUMMARY OF THE INVENTION

[0010] A floating gate for use in a memory cell is provided whichcomprises a first end region adjacent a first lateral end of thefloating gate; and a middle region positioned laterally toward a middleof the floating gate relative to the first end region, the middle regionhaving a vertical thickness which is less than a vertical thickness ofthe first end region; wherein the floating gate is composed of amaterial which is formed during a single fabrication step and shaped toform the first end region and middle region by one or more subsequentfabrication steps.

[0011] In one variation, the first end region and the middle region havetop surfaces which are substantially parallel to a plane of a substrateunderlying the floating gate, the top surfaces of the first end regionand middle region being connected to one another by a surface which issubstantially perpendicular to the plane of the substrate underlying thefloating gate.

[0012] In another variation, the floating gate further includes a firstsloped region positioned between the first end region and the middleregion. The first sloped region may be shaped to have a top surfacewhich is positioned at an angle between about 0 and 45 degrees relativeto a line perpendicular to a plane of a substrate underlying thefloating gate.

[0013] A floating gate for use in a memory cell is also provided whichcomprises a first end region adjacent a first lateral end of thefloating gate; a second end region adjacent a second lateral end of thefloating gate opposite the first lateral end; and a middle regionpositioned laterally between the first and second end regions, themiddle region having a vertical thickness which is less than a verticalthickness of the first end region and which is less than a verticalthickness of the second end region; wherein the floating gate iscomposed of a material which is formed during a single fabrication stepand shaped to form the first and second end regions and middle region byone or more subsequent fabrication steps.

[0014] In one variation, the first and second end regions and the middleregion have top surfaces which are substantially parallel to a plane ofa substrate underlying the floating gate, the top surfaces of the firstend region and middle region are connected to one another by a surfacewhich is substantially perpendicular to the plane of the substrateunderlying the floating gate and the top surfaces of the second endregion and middle region are connected to one another by a surface whichis substantially perpendicular to the plane of the substrate underlyingthe floating gate.

[0015] In another variation, the floating gate further includes a firstsloped region positioned between the first end region and the middleregion and a second sloped region positioned between the second endregion and the middle region. The first and second sloped regions may beshaped to have top surfaces which are positioned at an angle betweenabout 0 and 45 degrees relative to a line perpendicular to a plane of asubstrate underlying the floating gate.

[0016] According to the above embodiments, the first and second endregions and the middle region may have top surfaces which aresubstantially planar. The first and second end regions and middleregions may also have top surfaces which are substantially parallel to aplane of a substrate underlying the floating gate.

[0017] Also according to the above embodiments, the floating gatepreferably has a bottom surface facing a plane of a substrate underlyingthe floating gate, the floating gate being positioned substantiallywithin a lateral footprint defined by the bottom surface of the floatinggate.

[0018] Also according to the above embodiments, the first end region,middle region and second end region combined have a width of less thanone micron, and preferably less than about 0.5 micron.

[0019] In regard to each of the above floating gate embodiments, thefloating gate may be incorporated into a floating gate memory cellcomprising: a substrate; source and drain regions positioned over thesubstrate; an insulating layer positioned over the source and drainregions; the floating gate positioned over the insulating layer betweenthe source and drain regions; and a control gate positioned over thedielectric insulator.

[0020] Also provided according to the present invention are methods forfabricating the floating gates of the present invention. According toone embodiment, a method is provided for forming a contoured floatinggate for use in a floating gate memory cell the method including forminga floating gate comprising a polysilicon layer over a substrate; formingoxide layers on opposing sides of the floating gate, the oxide layerhaving a vertical thickness greater than a vertical thickness of thefloating gate; forming a spacer layer over the oxide layers and thefloating gate; removing a portion of the spacer layer such that sidewalls leave a top surface of the floating gate positioned laterallytoward a middle region of the floating gate is exposed; and removing aportion of the floating gate underlying the exposed top surface of themiddle region to form the contoured floating gate.

[0021] In one variation of the method, the floating gate includes afirst end region at a first lateral end of the floating gate and asecond end region at a second lateral end of the floating gate, wherethe spacer layer formed during the step of forming the spacer layer hasa vertical thickness at the first end region and a vertical thickness atthe second end region that are each greater than a vertical thickness ofthe spacer layer at the middle region.

[0022] In other variations, the floating gate includes a first endregion at a first lateral end of the floating gate and a second endregion at a second lateral end of the floating gate and wherein thefloating gate, after removing the portion of the floating gate, has avertical thickness at the middle region that is less than a verticalthickness of the floating gate at the first end region and less than avertical thickness of the floating gate at the second end region.

[0023] Still further, the step of forming the floating gate may includeplanarizing a top surface of the floating gate. The step of removing aportion of the floating gate may include forming a new top surface inthe middle region which is substantially parallel to the substrate. Thestep of removing a portion of the floating gate may also create arectangular shaped recess in the middle region of the floating gate. Thestep of removing a portion of the floating gate may alternatively createa recess in the floating gate having first and second sloped surfaces atangles less than 90° relative to the substrate, in which the first andsecond sloped surfaces may also be at angles between about 45° and 90°relative to the substrate. In still another variation, the step offorming the floating gate includes depositing the polysilicon layer anda masking layer over an insulating layer.

[0024] In regard to each of the above floating gate embodiments, amethod for forming a floating gate memory cell comprises the steps ofproviding a substrate; forming source and drain regions over thesubstrate; depositing an insulating layer over the source and drainregions; and forming a contoured floating gate positioned over theinsulating layer between the source and drain regions.

BRIEF DESCRIPTION OF THE FIGURES

[0025]FIG. 1 illustrates a memory cell according to the presentinvention.

[0026]FIG. 2 illustrates an embodiment of a memory cell of the presentinvention, with variations to the top surface of the floating gate shownin phantom.

[0027]FIG. 3A illustrates a floating gate with a shallow medial surface.

[0028]FIG. 3B illustrates a floating gate with a deep medial surface.

[0029]FIG. 3C illustrates a floating gate with a single raised end.

[0030] FIGS. 4A-4I illustrate an embodiment of a process for fabricatinga memory cell according to the present invention.

[0031]FIG. 4A illustrates a relatively thin tunnel oxide layer grownover a substrate.

[0032]FIG. 4B illustrates the polysilicon layer and masking layer beingetched away to form a pattern of columns.

[0033]FIG. 4C illustrates oxide structures being deposited between thecolumns so that each column is abutted by an oxide structure.

[0034]FIG. 4D illustrates the masking layer being removed to create astep topography between the polysilicon layer and the oxide structure.

[0035]FIG. 4E illustrates a spacer layer deposited over the steptopography comprising the columns and the oxide structures.

[0036]FIG. 4F illustrates the spacer layer etched back to selectivelyremove all of the spacer layer on top of the oxide structures.

[0037]FIG. 4G illustrates a portion of the floating gate formed by thepolysilicon layer is removed to form a new top surface to the middleregion.

[0038]FIG. 4H illustrates the oxide structure dipped back to shorten thetop surface of the oxide structure and to form a contoured top orcoupling surface on top of the polysilicon layer.

[0039]FIG. 4I illustrates the dielectric layer deposited over thepolysilicon layer and the oxide layer.

[0040]FIG. 5 illustrates a schematic of a non-volatile memory devicethat may be employed with this invention.

DETAILED DESCRIPTION

[0041] The present invention relates to a flash memory cell designhaving a reduced lateral dimension by utilizing a floating gate with acontoured coupling surface. The contoured coupling surface is created bytaking material for forming the floating gate and shaping the materialto form a floating gate which varies in thickness across its lateraldimension.

[0042] In one embodiment, the floating gate comprises a first end regionadjacent a first end of the floating gate and a middle region positionedtoward a middle of the floating gate relative to the first end regionwhich has a thickness which is less than a thickness of the first endregion.

[0043] In another embodiment, the floating gate comprises a first endregion adjacent a first end of the floating gate, a second end regionadjacent a second end of the floating gate, and a middle regionpositioned between the first and second end regions which has athickness which is less than a thickness of the first end region and athickness of the second end region.

[0044] In another embodiment, the floating gate comprises a first endregion adjacent a first end of the floating gate, a second end regionadjacent a second end of the floating gate, a middle region positionedbetween the first and second end regions which has a thickness which isless than a thickness of the first end region and a thickness of thesecond end region, a first sloped region positioned between the firstend region with the middle region, and a second sloped region positionedbetween the second end region with the middle region. In thisembodiment, the first and second sloped regions are preferably shaped tohave a top surface which is positioned at an angle between about 0 and45 degrees relative to a line perpendicular to a plane of a substrateunderlying the floating gate.

[0045] In regard to each of the above embodiments, the various regionsof the floating gate are formed of a material which is formed by asingle fabrication step. Subsequent to the material's formation, one ormore additional fabrication steps are employed to shape the floatinggate.

[0046] In regard to each of the above embodiments, the first and secondend regions preferably have a substantially planar top surface. Theplanar top surface of the end regions is preferably parallel to a planeof a substrate underlying the floating gate.

[0047] In regard to each of the above embodiments, the middle regionpreferably has a substantially planar top surface. The top surface ofthe middle region is also preferably parallel to a plane of a substrateunderlying the floating gate.

[0048] Also in regarding each of the above embodiments, the floatinggate is preferably substantially positioned within a lateral footprintdefined by a surface of the floating gate underlying the floating gate.Preferably the first end portion, middle portion and second end portioncombined in the lateral dimension are less than 1.0 micron wide and morepreferably less than 0.5 micron wide.

[0049] The present invention also relates to methods for fabricating afloating gate according to this invention. According to one embodiment,the method comprises forming a floating gate comprising a polysiliconlayer over a substrate; providing oxide layers on opposing sides of thefloating gate which have a vertical thickness that is greater than avertical thickness of the floating gate; forming a spacer layer over theoxide layers and the floating gate; removing a portion of the spacerlayer such that a top surface of the floating gate positioned laterallytowards a middle region of the floating gate is exposed; and removing aportion of the floating gate underlying the exposed top surfaces of themiddle region to form the contoured floating gate.

[0050] In another embodiment for fabricating a floating gate memorycell, the method comprises of providing a substrate, forming source anddrain regions over the substrate, depositing an insulating layer overthe source and drain regions, and forming a contoured floating gate thatis positioned over the insulating layer between the source and drainregions.

[0051] In regard to each of the embodiments for methods, the floatinggate may include a first and second end region adjacent to correspondinglateral ends, where the method includes forming a spacer layer to have avertical thickness at the first end region and a vertical thickness at asecond end region that are each greater than a vertical thickness of thespacer layer at a middle region of the floating gate.

[0052] In regard to each of the embodiments for methods, the floatinggate may be formed to have a vertical thickness at a middle region thatis less than a vertical thickness of the floating gate at the endregions.

[0053] As will be described in greater detail below, use of the floatinggate of the present invention provides significant advantages in that asmaller memory cell is provided with comparable performance to otherFLASH EPROM memory cells know in the art which have larger dimensions.Among other advantages, the memory cell of the present invention isinexpensive to manufacture, and avoids leakage of electrical charge fromthe floating gate.

[0054]FIG. 1 illustrates memory cells according to the invention alignedin a column to form a memory array or FLASH EPROM device. The memorycells in the column share a semiconductor substrate 110. The particulardesign or formation of the semiconductor substrate 110 may be varieddepending on the memory device architecture. For example, for thesource-drain-source configuration shown in FIG. 5, the semiconductorsubstrate 110 may include an n-type well 112 formed in a p-typesubstrate 108, as illustrated in FIG. 1. Within the substrate 110, adrain junction is formed by buried p-type drain diffusion region 114 andburied drain pocket 116. A source junction is formed by buried p-typesource diffusion region 109 and p-type buried source pocket 111.Alternative semiconductor substrates may also be employed with thisinvention, including using an n-type substrate with a p-type well andn-type diffusion regions.

[0055] A floating gate 120 is positioned over the semiconductorsubstrate 110, between the source 109 and drain 114 regions. Adielectric isolation layer 106 is positioned between the floating gates120 and the substrate. In a preferred embodiment, the dielectric layeris a tunnel oxide structure. The floating gates 120 are spaced-apart,with oxide structures 126 disposed over an oxide region 145 of thesemiconductor substrate 110 and preferably on the tunnel oxide layer106. Likewise, the floating gates 120 are positioned over a floatinggate region 125 of the semiconductor substrate 110 and preferably on thetunnel oxide layer 106. As illustrated in FIG. 1, the floating gate 120extends laterally in a word line direction. Additional floating gatesthat comprise the FLASH EPROM of this invention may extend into thepaper in a bit-line direction and are not shown by FIG. 5.

[0056] Each floating gate includes a top coupling surface extending thewidth of the floating gate. A control gate 150 is formed over thefloating gate 120 to which the floating gate 120 is electrically orcapacitively coupled. The control gate 150 may extend over adjacentoxide structures 126.

[0057] Another dielectric layer may be disposed between the control gate150 and the floating gates 120. In a preferred embodiment, thedielectric layer is an oxide-nitride-oxide layer (ONO) 134, and thecontrol gate 150 is formed from a second layer of polysilicon 140combined with a tungsten-silicon (WSi_(x)) layer 160. The floating gate120 is preferably formed from a uniform polysilicon body.

[0058] The design of floating gates used in the present invention willnow be described in greater detail. FIG. 2 illustrates an embodiment ofa floating gate according to the present invention. As illustrated, thefloating gate 120 may be divided into five regions moving left to right:a first end region 201, a first sloped region 202, a middle region 203,a second sloped region 204, and a second end region 205. As illustrated,the thickness of the floating gate 120 varies between these differentregions to create a top coupling surface 130 with a contouredtopography.

[0059] In the contoured topography, the first and second end regionsform raised first and second end surfaces 218 and 224. The floating gateat the middle region 103 is vertically thinner than the end regions andthus forms a recessed middle surface 222. The raised end surfaces 218and 224 may be aligned over the floating gate region 125 of thesemiconductor substrate 110, and preferably over the first and secondend regions 201 and 205. The diffusion regions are preferably positionedat the oxide regions 145 adjacent to the first and second end regions201 and 205. In a preferred embodiment, the raised end surfaces 218, 224form plateaus that are parallel to the substrate 110. The raised endsurfaces 218, 224 are preferably substantially perpendicular to firstand second sides 228, 238.

[0060] The floating gate at the first and second sloped regions 202, 204has a vertical thickness which varies between the thickness of the firstor second end region and the thickness of the middle region. Theseregions form first and second sloped surfaces 236, 237 that extend fromthe first and second end surfaces 218, 224 respectively to the middlesurface 222, or 222′. It is noted that when the first and second slopedsurfaces 236, 237 are perpendicular to the substrate, the first andsecond sloped regions are very narrow.

[0061] In a preferred embodiment, the sloped surfaces 236, 237 aresubstantially planar as they extend from the first and second endsurfaces 218, 224 to the middle surface 222. The middle surface 222 ispreferably substantially parallel to the semiconductor substrate 110.

[0062] It is noted that the middle surface 222, or 222′ may be recessedto different depths relative to the raised end surfaces 218, 224. As aresult, the angle of the sloped surfaces 236, 237 relative to a line 239extending perpendicular from the substrate may be varied. For example,as illustrated in an embodiment of FIG. 3A, the middle surface 322 isnot very deep. In this instance, the sloped surfaces 336, 337 are at anangle greater than 45 degrees relative to the perpendicular. Asillustrated in another embodiment of FIG. 3B, the middle surface 322 maybe recessed deeper relative to the raised end surfaces 318, 324. In thisinstance, the sloped surfaces 336, 337 are at an angle less than 45degrees relative to the perpendicular. In a preferred embodiment, theangle of the sloped middle borders is between 45 and 90 degrees. Asillustrated in FIG. 3C, when the first and second sloped surfaces 336,337 are perpendicular to the substrate, the first and second slopedregions are very narrow. The manufacturing process for positioning themiddle surface 322 will be described further below.

[0063] The width of the floating gate is preferably between about 2,000and 10,000 Angstroms. The first and second end regions preferably have athickness between about 1,000 and 9,000 Angstroms. When the floatinggate includes both a first and second end region, the first and secondend regions 201, 205 are preferably separated from each other by 0.4microns and alternatively by 0.2 microns. The tunnel oxide layer 106 ispreferably between about 50 and 120 Angstroms in thickness. The floatinggate poly 104 is preferably between 2,000 and 10,000 Angstroms thick.Further details, variations, and alternatives to the embodimentsmentioned above will be made clearer in the discussion below, detailed aprocess flow for this invention.

[0064] FIGS. 4A-4I illustrate an embodiment of a process for fabricatinga memory cell according to the present invention, and more specifically,an array of floating gates. As illustrated in FIG. 4A, a relatively thintunnel oxide layer 406 is grown over a substrate 400. In an embodimentsuch as the one shown by FIG. 5, the substrate includes a p-typesubstrate 408 and an n-type well 412. Next, a conductive layer forforming a floating gate such as a polysilicon layer 420 is depositedover the tunnel oxide layer 406, followed by a masking layer 410. Themasking layer 410 is preferably Si₃N₄, and serves to create an alignmentstructure for a second masking layer or spacer layer deposited on thesubstrate at an intermediate manufacturing step (illustrated in FIG.4E). In view of the high etching selectivity between Si₃N₄ andpolysilicon, use of Si₃N₄ allows the masking layer 410 to be etched awayfrom the memory cell structure without requiring a stop layer to protectthe polysilicon layer. Alternative materials to Si₃N₄ for the maskinglayer include polysilicon film. However, using polysilicon film as themasking layer requires using a liner film over the polysilicon layer 420to provide a stop layer for when the masking layer is eventuallyremoved.

[0065] As illustrated in FIG. 4B, the polysilicon layer 420 and maskinglayer 410 are etched away to form a pattern of columns 430. In thisstep, dopants are used to create diffusion regions 415 between thecolumns 430. This may be accomplished using conventional ionimplantation methods, although chemical or other similar processes mayalso be employed. Preferable, a p-type dopant is employed to create thediffusion regions, such as arsenic (As) is implanted into the substrate400. Other suitable dopants include phosphorous (P).

[0066] In FIG. 4C, oxide structures 420 are deposited between thecolumns 430, so that each column is abutted by an oxide structure. Eachoxide structure 440 is preferably resistant to etch attacks fromsubsequent etching of either the polysilicon layer 420 or masking layer410 described in the subsequent steps. The oxide structure 440 serves toinsulate the polysilicon layers 420, while providing an etch stop layerin the word-line direction. By insulated the polysilicon layers 420, theoxide structures 440 prevent leakage of electrons from the floatinggate, as well as from the diffusion regions of the substrates. Inaddition, the oxide structures 440 decrease the drain coupling ratio(DCR), thereby increasing the coupling ratio of the memory cell. Thevertical thickness of each oxide structure 440 is preferably on theorder of 1500 Angstroms. After the oxide structures 440 are deposited, atopology comprising the oxide structures and the columns 430 isplanarized by chemical mechanical polishing (CMP). Alternatively, thetop surface may be planarized by using an etch back process.

[0067] As illustrated in FIG. 4D, the masking layer 410 is then removedto create a step topography between the polysilicon layer 420 and theoxide structure 440, as shown by cavities 445. The step topography formsa self-alignment structure for an oxide spacer to be subsequentlydeposited in a subsequent step. The polysilicon layer 420 may then bereferenced with respect to lateral ends 422, 423 that abut or areadjacent to the oxide structures 440, end regions 424, 425 adjacent tothe lateral ends, and a middle region 426 between the end regions.

[0068]FIG. 4E shows that a spacer layer 450 is deposited over the steptopography comprising the columns 430 and the oxide structures 440.Preferably, the spacer layer 450 is a chemical vapor deposited (CVD)oxide formed from SiO₂, or alternatively Si_(x)O_(y). Alternatively, thespacer layer 450 may be a high density plasma oxide, a film deposited bydecomposition of tetraethyl orthosilicate (TEOS) or other similarlyformed oxides such as SiH₄ oxides. More generally, spacer layer 450 maybe an etchable material having high selectively with the underlyingpolysilicon layer, such as Si₃N₄. In one embodiment, the thickness ofthe spacer layer 450 ranges in general between 500-4000 Angstroms overthe oxide structures 440.

[0069] As illustrated in FIG. 4F, the spacer layer 450 is etched back toselectively remove all of the spacer layer on top of the oxidestructures 440. Preferably, the etching method employed has highselectivity to the spacer layer 450 so that the spacer layer may beetched away from the oxide structure 440 without removal of the adjacentpolysilicon layer 420. Therefore, in a preferred embodiment, the spacerlayer 450 has a selectivity ratio with the polysilicon layer 420 ofapproximately 40:1. The spacer layer 450 bordering the cavities 445 isalso partially removed during the etch back so that remaining spacerlayers 255 at the end regions form sidewalls 455. The sidewalls 455extend vertically from the top of the column 430 along a verticalsurface 485 formed by the oxide structure 440 abutting the column. Apolysilicon surface 465 may be exposed between the sidewalls 455.Etching the spacer layer 450 as described in this paragraph allows theresulting topography at this intermediate step to be relatively flat atthe oxide structure 440 and, if so desired, at the polysilicon surface465 exposed between the oxide structures. As will be further describedfor this preferred embodiment, the width of the sidewalls 455 in theword-line direction corresponds or correlates to the width of the raisedend surfaces 118, 124 for the floating gate 120 shown in FIG. 1.Therefore, the width of the sidewalls 455 may be set during themanufacturing process to also form the eventual slope or wordline lengthof the middle surface 122 and/or middle border 136 shown in FIG. 1. Assuch, the width of the sidewalls 455 implement a desired coupling ratiofor the memory cell formed by this process. In order to maximize thecoupling surface of the floating gate, the width of the sidewalls isless than 0.4 μm, preferably, and may still be smaller depending on theneeds of the application.

[0070] As illustrated in FIG. 4G, a portion of the floating gate formedby the polysilicon layer 240 is removed to form a new top surface to themiddle region. Preferably, this is accomplished by etching back thepolysilicon layer 420 to form a new polysilicon exposed surface 465′.Due to the high selectivity between the material chosen for the spacerlayer 450 and the polysilicon layer 420, the spacer oxide sidewalls 455are not affected by further etching between the sidewalls 455. Use ofthe spacer layer 450 provides another advantage to this invention duringthe etch outlined in this and the preceding step, in that the spacerlayer 450 maintains the planarity of top surfaces of end regions, 424,425 corresponding to raised end surfaces 118, 124 of FIG. 1. In thisway, raised end surfaces 118, 124 formed during this step avoid sharppeaks and corners present in prior art memory devices employing floatinggates with reduced lateral dimensions. Elimination of sharp peaks andcorners reduce the leakage and electron instability associated withpeaks and corners of the floating gate.

[0071] In FIG. 4H, the oxide structure 440 is dipped back to shorten thetop surface of the oxide structure and to form a contoured top orcoupling surface 475 on top of the polysilicon layer 420. Preferably,the oxide structure 440 is dipped back by a buffer oxide etch dip havinga selectivity ratio between 10:1 and 50:1, with a particular preferredembodiment having a selectivity ratio of 40:1. In a preferredembodiment, the resulting coupling surface 475 formed by this process isshaped to provide the raised end surfaces 118, 124 of the floating gate120 shown in FIG. 1. In this manner, a preferred fabrication process maybe used to fabricate a floating gate 120 of FIG. 1, where the recessedmiddle surface 122 and raised ends 118 and 124 combine to provideadditional surface area to the coupling surface to increase the couplingratio between the floating gate 120 and the control gate 150.

[0072] As illustrated in FIG. 4I, dielectric layer 470 is deposited overthe polysilicon layer 420 and the oxide layer 440. Preferably, thedielectric layer 470 is an oxide-nitride-oxide (ONO) layer. In apreferred embodiment, the ONO layer comprises a high temperature oxidedeposited by CVD, a CVD nitride and another high temperature oxidedeposited by CVD. In this preferred embodiment, the thickness of thefirst oxide layer is 62 Angstroms, the thickness of the nitride layer is62 Angstroms, and the thickness of the bottom oxide layer is 45Angstroms. The deposition of the second dielectric layer is followed bydeposition of a second polysilicon layer 472, and WSI_(x) 474, whichcombine to form the control gate.

[0073] To complete the memory device, conventional flash memoryfabrication steps are performed. In a preferred embodiment, theresulting memory array includes a bit-line pitch of 0.95μm, and aword-line pitch of 0.4 μm. In variations of the present invention,individual cell sizes may be further reduced in dimensions by reducingthe pitch between individual memory cells. For example, the oxidestructures 440 (or 126 in FIG. 1) may be clipped in the word-linedirection to provide an open region on top of the tunnel oxide layer forreceiving boron phosphosilicate glass (BSPG), as disclosed in “A 0.24-μmCell Process With 0.18-μm Width Isolation and 3D Interpoly DielectricFilms for 1-GB Flash Memories” by Kobayashi et al., and incorporated byreference herein.

[0074]FIG. 5 illustrates a memory device architecture within which thememory cells of the present invention may be used. As illustrated,two-dimensional array of memory cells is formed by arranging floatinggate transistors into rows and columns. A right column comprisestransistors 500 and 506. A left column comprises transistors 502 and504. The first row of the array comprises transistors 502 and 500. Thesecond row of the array comprises transistors 504 and 506. The sourcesof transistors are connected to buried bit-line 514. The drain oftransistors 502 and 504 are connected to buried bit-line 512. The gatesof transistors 500 and 502 are connected to word-line 508. The gates ofthe transistors 504 and 506 are connected to word-line 510.

[0075] An X-Y addressing system is affected by word-line 508 and 510 andthe rows of memory cells that select on an X-axis and the bit-lines 512and 516 and the columns of memory cells on a Y-axis. When a memory cellsuch as 502 is addressed, appropriate voltages must be passed on to itsdrain and source by the bit-lines 512 and 514, respectively, and to itscontrol gate via word-line 508. In this manner, any cell in the arraymay be addressed individually for programming, erasure, and readoperations.

[0076] Alternative memory array device architectures may also be usedwith this invention. For example, U.S. Pat. No. 5,696,019 to Chang,incorporated herein by reference, discloses a memory device architecturesuitable with this invention comprising a plurality of columns of memorycells sharing one or more bit lines. The architecture is based on asource-drain cell configuration in which each column of cells has asingle buried diffusion local source line. An isolation structure suchas a trench oxide is positioned between each column of cells.

[0077] Memory cells of the present invention may be programmed byproviding a positive voltage to the control gate and a negative voltageto the buried drain diffusion, while the buried p-type source diffusionis allowed to float. Under these conditions, electrons may tunnel fromthe valence band to the conduction band, leaving free holes in thevalance bands. The positive voltage at the control gate attractselectrons towards the floating gate. The electrons are accelerated inthe strong vertical electrical field between the drain diffusion and thecontrol gate and a number of them become “hot” electrons with sufficientenergy to be injected through a tunneling dielectric layer 106 (as shownby FIG. 1) into the floating gate 120 (FIG. 1).

[0078] Erasure is accomplished by F-N tunneling from the floating gateto the buried p-type source diffusion region. During erasure, a negativevoltage is applied to the control gate, a positive voltage is applied tothe source diffusion, and the drain is floating. Under these conditions,a forward bias will be imposed on the source diffusion and the n-well sothat the n-well is positively charged. As a result, F-N tunnelingerasure of electrons from the floating gate to a channel will takeplace.

[0079] Reading is accomplished by providing a negative voltage to thedrain diffusion and a negative voltage to the control gate, with thesource at 0 volts. When the floating gate is charged, the thresholdvoltage for causing the p-channel transistor to conduct is decreasedbelow the voltage applied to the control gate during a read operation.Thus a charged transistor will conduct during a read operation and anuncharged transistor will not conduct. The non-conducting state of thecell can be interpreted as a binary 1 or 0 depending on the polarity ofthe sensing circuitry.

[0080] The voltages required for programming, erasing, and/or readingoperations depends in part on a coupling ratio between the floating gateand the control gate of the memory cell. The voltage across the floatinggate may be characterized by the following equation:

V _(FG) =V _(CG) [C _(CR)(C _(CR) +C _(K))]

[0081] In the above equation, C_(CR) is the capacitive couple ratiobetween the floating gate and the control gate. The factor C_(K)represents the capacitive coupling of the floating gate across thetunnel oxide layer 206 for programming, erasing, or reading. As theabove equation shows, the higher the coupling ratio between the floatinggate and the control gate, the more equal the voltage across thefloating gate is compared to the voltage across the control gate. Assuch, increasing the coupling ratio between the floating gate and thecontrol gate decreases the voltage required to effectuate programming,erasing, or reading.

[0082] Some memory devices of the known art provide the floating gatewith a greater coupling surface in order to increase the coupling ratiobetween the floating gate and the control gate. This has previously beenaccomplished by enlarging the lateral dimensions of the floating gate onthe substrate. As such, the floating gates of the known art occupy asignificant percentage of the real estate allocated on the memory arraydevice. By contrast, this invention provides a comparable floating gatebut having reduced lateral dimensions. More specifically, this inventionprovides for a floating gate having reduced later dimensions but whichmaintains or increases the coupling ratio between the floating gate andthe control gate.

[0083] The foregoing description of a preferred embodiment of theinvention has been presented for purposes of illustration anddescription. It is not intended to be exhaustive or to limit theinvention to the precise forms disclosed. Obviously, many modificationsand variations will be apparent to practitioners skilled in this art. Itis intended that the scope of the invention be defined by the followingclaims and their equivalents.

What is claimed is:
 1. A method for forming a contoured floating gatefor use in a floating gate memory cell, the method comprising: forming afloating gate comprising a polysilicon layer over a substrate; formingoxide layers on opposing sides of the floating gate, the oxide layerhaving a vertical thickness greater than a vertical thickness of thefloating gate; forming a spacer layer over the oxide layers and thefloating gate; removing a portion of the spacer layer such that a topsurface of the floating gate positioned laterally toward a middle regionof the floating gate is exposed; and removing a portion of the floatinggate underlying the exposed top surface of the middle region to form thecontoured floating gate.
 2. The method of claim 1, wherein the floatinggate includes a first end region at a first lateral end of the floatinggate and a second end region at a second lateral end of the floatinggate, and wherein the spacer layer formed during the step of forming thespacer layer has a vertical thickness at the first end region and avertical thickness at the second end region that are each greater than avertical thickness of the spacer layer at the middle region.
 3. Themethod of claim 1, wherein the floating gate includes a first end regionat a first lateral end of the floating gate and a second end region at asecond lateral end of the floating gate and wherein the floating gate,after removing the portion of the floating gate, has a verticalthickness at the middle region that is less than a vertical thickness ofthe floating gate at the first end region and less than a verticalthickness of the floating gate at the second end region.
 4. The methodof claim 1, wherein the step of forming the floating gate includesplanarizing a top surface of the floating gate.
 5. The method of claim1, wherein the step of removing a portion of the floating gate includesforming a new top surface in the middle region which is substantiallyparallel to the substrate.
 6. The method of claim 1, wherein the step ofremoving a portion of the floating gate creates a rectangular shapedrecess in the middle region of the floating gate.
 7. The method of claim1, wherein the step of removing a portion of the floating gate creates arecess in the floating gate having first and second sloped surfaces atangles less than 90° relative to the substrate.
 8. The method of claim7, wherein the first and second sloped surfaces are at angles betweenabout 45° and 90° relative to the substrate.
 9. The method of claim 1,wherein the step of forming the floating gate includes depositing thepolysilicon layer and a masking layer over an insulating layer.
 10. Themethod of claim 9, wherein the step of forming the floating gateincludes etching a plurality of columns comprising the polysilicon layerand the masking layer.
 11. The method of claim 10, wherein the step offorming the floating gate includes removing the masking layer from theplurality of columns.
 12. The method of claim 9, wherein the maskinglayer comprises silicon nitride.
 13. The method of claim 10, wherein thestep of forming oxide layers includes depositing the oxide layersbetween each column comprising the polysilicon layer and the maskinglayer, and planarizing the oxide layers and the columns prior toremoving the masking layer so that the vertical thickness of the oxidelayer is greater than the vertical thickness of the floating gate. 14.The method of claim 1, wherein the spacer layer comprises a materialselected from polysilicon, tetraethyl orthosilicate, and siliconnitride.
 15. The method of claim 1, wherein the step of removing theportion of the floating gate underlying the exposed middle surfaceincludes removing the spacer layer from the oxide layer and the middlesurface of the floating gate in a single etch so as to expose the middlesurface of the floating gate while maintaining the spacer layer overfirst end and second end regions of the floating gate.
 16. The method ofclaim 15, wherein the step of removing a portion of the floating gatetop includes etching the middle region of the floating gate.
 17. Amethod for forming a floating gate memory cell, the method comprising:providing a substrate; forming source and drain regions over thesubstrate; depositing an insulating layer over the source and drainregions; and forming a contoured floating gate positioned over theinsulating layer between the source and drain regions, the floating gatebeing formed by forming a floating gate comprising a polysilicon layerover a substrate, forming oxide layers on opposing sides of the floatinggate, the oxide layer having a vertical thickness greater than avertical thickness of the floating gate, forming a spacer layer over theoxide layers and the floating gate, removing a portion of the spacerlayer such that a middle surface of the floating gate positionedlaterally toward a middle of the floating gate is expose, and removing aportion of the floating gate underlying the exposed middle surface toform the contoured floating gate; and forming a dielectric layer overthe contoured floating gate.
 18. The method of claim 17, wherein thefloating gate includes a first end region at a first lateral end of thefloating gate and a second end region at a second lateral end of thefloating gate, and wherein the spacer layer formed during the step offorming the spacer layer has a vertical thickness at the first endregion and a vertical thickness at the second end region that are eachgreater than a vertical thickness of the spacer layer at the middleregion.
 19. The method of claim 17, wherein the floating gate includes afirst end region at a first lateral end of the floating gate and asecond end region at a second lateral end of the floating gate andwherein the floating gate, after removing the portion of the floatinggate, has a vertical thickness at the middle region that is less than avertical thickness of the floating gate at the first end region and lessthan a vertical thickness of the floating gate at the second end region.20. The method of claim 17, wherein the step of forming the floatinggate includes planarizing a top surface of the floating gate.
 21. Themethod of claim 17, wherein the step of removing a portion of thefloating gate includes forming a new top surface in the middle regionwhich is substantially parallel to the substrate.
 22. The method ofclaim 17, wherein the step of removing a portion of the floating gatecreates a rectangular shaped recess in the middle region of the floatinggate.
 23. The method of claim 17, wherein the step of removing a portionof the floating gate creates a recess in the floating gate having firstand second sloped surfaces at angles less than 90° relative to thesubstrate.
 24. The method of claim 23, wherein the first and secondsloped surfaces are at angles between about 45° and 90° relative to thesubstrate.
 25. The method of claim 17, wherein the step of forming thefloating gate includes depositing the polysilicon layer and a maskinglayer over an insulating layer prior to forming the floating gate. 26.The method of claim 25, wherein the step of forming the floating gateincludes etching a plurality of columns comprising the polysilicon layerand the masking layer.
 27. The method of claim 26, wherein the step offorming the floating gate includes removing the masking layer from theplurality of columns.
 28. The method of claim 25, wherein the maskinglayer comprises silicon nitride.
 29. The method of claim 26, wherein thestep of forming oxide layers includes depositing the oxide layersbetween each column comprising the polysilicon layer and the maskinglayer, and planarizing the oxide layers and the columns prior toremoving the masking layer so that the vertical thickness of the oxidelayer is greater than the vertical thickness of the floating gate. 30.The method of claim 17, wherein the spacer layer comprises a materialselected from polysilicon, tetraethyl orthosilicate, and siliconnitride.
 31. The method of claim 17, wherein the step of removing theportion of the floating gate underlying the exposed middle surfaceincludes removing the spacer layer from the oxide layer and the middlesurface of the floating gate in a single etch so as to expose the middlesurface of the floating gate while maintaining the spacer layer overfirst end and second end regions of the floating gate.
 32. The method ofclaim 17, wherein the step of removing a portion of the floating gatetop includes etching the middle region of the floating gate.
 33. In afloating gate memory cell, a floating gate comprising: a first endregion adjacent a first lateral end of the floating gate; and a middleregion positioned laterally toward a middle of the floating gaterelative to the first end region, the middle region having a verticalthickness which is less than a vertical thickness of the first endregion; wherein the floating gate is composed of a material which isformed during a single fabrication step and shaped to form the first endregion and middle region by one or more subsequent fabrication steps.34. A floating gate according to claim 33 wherein the first end regionand the middle region have top surfaces which are substantially parallelto a plane of a substrate underlying the floating gate, the top surfacesof the first end region and middle region being connected to one anotherby a surface which is substantially perpendicular to the plane of thesubstrate underlying the floating gate.
 35. A floating gate according toclaim 33 wherein the floating gate further includes a first slopedregion positioned between the first end region and the middle region.36. A floating gate according to claim 35 wherein the first slopedregion is shaped to have a top surface which is positioned at an anglebetween about 0 and 45 degrees relative to a line perpendicular to aplane of a substrate underlying the floating gate.
 37. A floating gateaccording to claim 33 wherein the first end region has a top surfacewhich is substantially planar.
 38. A floating gate according to claim 33wherein the first end region has a top surface which is substantiallyparallel to a plane of a substrate underlying the floating gate.
 39. Afloating gate according to claim 33 wherein the middle region has asubstantially planar top surface.
 40. A floating gate according to claim33 wherein the middle region has a top surface which is substantiallyparallel to a plane of a substrate underlying the floating gate.
 41. Afloating gate according to claim 33 wherein the floating gate has abottom surface facing a plane of a substrate underlying the floatinggate, the floating gate being positioned substantially within a lateralfootprint defined by the bottom surface of the floating gate.
 42. In afloating gate memory cell, a floating gate comprising: a first endregion adjacent a first lateral end of the floating gate; a second endregion adjacent a second lateral end of the floating gate opposite thefirst lateral end; and a middle region positioned laterally between thefirst and second end regions, the middle region having a verticalthickness which is less than a vertical thickness of the first endregion and which is less than a vertical thickness of the second endregion; wherein the floating gate is composed of a material which isformed during a single fabrication step and shaped to form the first andsecond end regions and middle region by one or more subsequentfabrication steps.
 43. A floating gate according to claim 42 wherein thefirst and second end regions and the middle region have top surfaceswhich are substantially parallel to a plane of a substrate underlyingthe floating gate, the top surfaces of the first end region and middleregion are connected to one another by a surface which is substantiallyperpendicular to the plane of the substrate underlying the floating gateand the top surfaces of the second end region and middle region areconnected to one another by a surface which is substantiallyperpendicular to the plane of the substrate underlying the floatinggate.
 44. A floating gate according to claim 33 wherein the floatinggate further includes a first sloped region positioned between the firstend region and the middle region and a second sloped region positionedbetween the second end region and the middle region.
 45. A floating gateaccording to claim 44 wherein the first and second sloped regions areshaped to have top surfaces which are positioned at an angle betweenabout 0 and 45 degrees relative to a line perpendicular to a plane of asubstrate underlying the floating gate.
 46. A floating gate according toclaim 43 wherein the first and second end regions have top surfaceswhich are substantially planar.
 47. A floating gate according to claim43 wherein the first and second end regions have top surfaces which aresubstantially parallel to a plane of a substrate underlying the floatinggate.
 48. A floating gate according to claim 43 wherein the middleregion has a substantially planar top surface.
 49. A floating gateaccording to claim 44 wherein the middle region has a top surface whichis substantially parallel to a plane of a substrate underlying thefloating gate.
 50. A floating gate according to claim 43 wherein thefloating gate has a bottom surface facing a plane of a substrateunderlying the floating gate, the floating gate being positionedsubstantially within a lateral footprint defined by the bottom surfaceof the floating gate.
 51. A floating gate memory cell comprising: asubstrate; source and drain regions positioned over the substrate; aninsulating layer positioned over the source and drain regions; afloating gate positioned over the insulating layer between the sourceand drain regions, the floating gate comprising a first end regionadjacent a first lateral end of the floating gate, and a middle regionpositioned laterally toward a middle of the floating gate relative tothe first end region, the middle region having a vertical thicknesswhich is less than a vertical thickness of the first end region, whereinthe floating gate is composed of a material which is formed during asingle fabrication step and shaped to form the first end region andmiddle region by one or more subsequent fabrication steps; and a controlgate positioned over the dielectric insulator.
 52. A floating gateaccording to claim 51 wherein the first end region and the middle regionhave top surfaces which are substantially parallel to a plane of asubstrate underlying the floating gate, the top surfaces of the firstend region and middle region being connected to one another by a surfacewhich is substantially perpendicular to the plane of the substrateunderlying the floating gate.
 53. A floating gate according to claim 51wherein the floating gate further includes a first sloped regionpositioned between the first end region and the middle region.
 54. Afloating gate according to claim 53 wherein the first sloped region isshaped to have a top surface which is positioned at an angle betweenabout 0 and 45 degrees relative to a line perpendicular to a plane of asubstrate underlying the floating gate.
 55. A floating gate according toclaim 51 wherein the first end region has a top surface which issubstantially planar.
 56. A floating gate according to claim 51 whereinthe first end region has a top surface which is substantially parallelto a plane of a substrate underlying the floating gate.
 57. A floatinggate according to claim 51 wherein the middle region has a substantiallyplanar top surface.
 58. A floating gate according to claim 51 whereinthe middle region has a top surface which is substantially parallel to aplane of a substrate underlying the floating gate.
 59. A floating gateaccording to claim 51 wherein the floating gate has a bottom surfacefacing a plane of a substrate underlying the floating gate, the floatinggate being positioned substantially within a lateral footprint definedby the bottom surface of the floating gate.
 60. A floating gate memorycell comprising: a substrate; source and drain regions positioned overthe substrate; an insulating layer positioned over the source and drainregions; a floating gate positioned over the insulating layer betweenthe source and drain regions, the floating gate comprising a first endregion adjacent a first lateral end of the floating gate; a second endregion adjacent a second lateral end of the floating gate opposite thefirst lateral end, and a middle region positioned laterally between thefirst and second end regions, the middle region having a verticalthickness which is less than a vertical thickness of the first endregion and which is less than a vertical thickness of the second endregion, wherein the floating gate is composed of a material which isformed during a single fabrication step and shaped to form the first andsecond end regions and middle region by one or more subsequentfabrication steps; and a control gate positioned over the dielectricinsulator.
 61. A floating gate according to claim 60 wherein the firstand second end regions and the middle region have top surfaces which aresubstantially parallel to a plane of a substrate underlying the floatinggate, the top surfaces of the first end region and middle region areconnected to one another by a surface which is substantiallyperpendicular to the plane of the substrate underlying the floating gateand the top surfaces of the second end region and middle region areconnected to one another by a surface which is substantiallyperpendicular to the plane of the substrate underlying the floatinggate.
 62. A floating gate according to claim 60 wherein the floatinggate further includes a first sloped region positioned between the firstend region and the middle region and a second sloped region positionedbetween the second end region and the middle region.
 63. A floating gateaccording to claim 62 wherein the first and second sloped regions areshaped to have top surfaces which are positioned at an angle betweenabout 0 and 45 degrees relative to a line perpendicular to a plane of asubstrate underlying the floating gate.
 64. A floating gate according toclaim 60 wherein the first and second end regions have top surfaceswhich are substantially planar.
 65. A floating gate according to claim60 wherein the first and second end regions have top surfaces which aresubstantially parallel to a plane of a substrate underlying the floatinggate.
 66. A floating gate according to claim 60 wherein the middleregion has a substantially planar top surface.
 67. A floating gateaccording to claim 60 wherein the middle region has a top surface whichis substantially parallel to a plane of a substrate underlying thefloating gate.
 68. A floating gate according to claim 60 wherein thefloating gate has a bottom surface facing a plane of a substrateunderlying the floating gate, the floating gate being positionedsubstantially within a lateral footprint defined by the bottom surfaceof the floating gate.